An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every memory location includes one or more status bits which maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicate whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing).
Once information is stored in a memory location, it is found by comparing every bit in memory with data in the comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, the local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a “match” indication. Otherwise, the CAM device returns a “no-match” indication. In addition, the CAM may return the identification of the address location in which the desired data is stored or one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back the address if there is a match found in memory.
FIG. 1 is a circuit diagram showing a conventional DRAM-based CAM cell 100, which includes two one-transistor (1T) DRAM cells 110a and 110b, and a four-transistor comparator circuit 120 made up of transistors Q2 through Q6. DRAM cells 110a and 110b are used to store values. Generally, the content of cell 110a is the logical NOT of the content of cell 110b. However, the cells 110a, 110b may also store the same values, i.e., “1”, “1”, or “0”, “0”, so that the CAM cell is respectively set to “always match” or “always mismatch” states. DRAM cell 110a includes transistor Q1 and a capacitor CA, which combine to form a storage node A that receives a data value from bit line BL1 at node U during write operations, and applies the stored data value to the gate terminal of transistor Q2 of comparator circuit 120. Transistor Q2 is connected in series with transistor Q3, which is controlled by a data signal transmitted on data line D1, between a match line M and a discharge line D. The second DRAM cell 110b includes transistor Q3 and a capacitor CB, which combine to form a storage node B that receives a data value from bit line BL2 at node V, and applies the stored data value to the gate terminal of transistor Q4 of comparator circuit 120. Transistor Q4 is connected in series with transistor Q5, which is controlled by a data signal transmitted on inverted data line D1#, between the match line and the discharge line.
FIG. 2 is a block diagram of a portion of a CAM device 200 which includes a plurality of CAM cells, such as the CAM cell 100 of FIG. 1. For purposes of simplicity, only a portion of the CAM device 200 is illustrated. In particular, some well known components, such as the previously discussed comparand register, control logic, and I/O logic are not illustrated. The device 200 includes two arrays 210a, 210b of CAM cells 100. Each array 210a, 210b includes its own bit lines (e.g., BL11–BL16 for array 210a, BL21–BL26 for array 210b) and word lines (e.g., WL11–WL13 for array 210a). Each word line WL11–WL13, WL21–WL23 is coupled a respective word line driver 220a, 220b. Similarly, each bit line is also coupled to respective bit line drivers (not illustrated). The CAM device 200 also includes a plurality of sense amplifiers 230. Each sense amplifier 230 is coupled to the CAM cells 100 of two separate bit lines (e.g., bit lines BL11, BL21) from two different arrays. This type of architecture, where a sense amplifier is coupled to bit lines from different arrays, is known as an open bit line architecture.
Now referring back to FIG. 1, in order perform a write operation upon a CAM cell, the data values (which are complements) to be stored are respectively written to dynamic storage nodes A and B by applying appropriate voltage signals (e.g., Vcc for logical ‘1’ or ground for logical ‘0’) on bit lines BL11 and BL21, and then applying a high voltage signal on word lines WL1 and WL2. The high voltage on word lines WL1 and WL2 turn on transistor Q1 and Q2, thereby passing the voltage signals to dynamic storage nodes A and B. Refresh circuitry (not illustrated), periodically refreshes the charges stored in capacitors CA and CB, so the data does not decay over time.
In order to perform a match operation, the data stored at nodes A and B are respectively applied to the gate terminals of transistors Q2 and Q5 of comparator circuit 120. Comparator circuit 120 is utilized to perform match (comparison) operations by, for example, precharging the match line M, grounding the discharge line D, and transmitting an applied data value and its complement respectively on data lines D1 and D1# to the gate terminals of transistor Q3 and Q6, respectively. A no-match condition is detected when match line M is discharged to ground through the signal path formed by transistors Q2 and Q3 and the discharge line D, or through the signal path formed by transistors Q5 and Q6 and the discharge line D. For example, when the stored data value at node A and the applied data value transmitted on data line D1# are both logic “1”, then both transistors Q2 and Q3 are turned on to discharge match line M to the discharge line (e.g., ground). When a match condition occurs, match line M remains in its pre-charged state (i.e., no signal path is formed by transistors Q2 and Q3, or transistors Q5 and Q6).
In order to perform a read operation, data stored as a charge level in the capacitors CA, CB of one of the dynamic storage nodes A, B of the CAM cell 100 is sensed using an associated sense amplifier 230 (FIG. 2) which compares the voltage level of a bit line coupled to one of the dynamic storage nodes (known as the active bit line) with the voltage level of a bit line not coupled to any dynamic storage nodes (known as the reference bit line). For example, node A of the CAM cell 100 which appears as the top left CAM cell illustrated in FIG. 2 can be sensed by first precharging two bit lines. The two bit lines to be precharged would include the bit line BL11 which will couple the CAM cell 100 to the sense amplifier 230 (i.e., the active bit line), as well as the other bit line BL21 coupled to the same sense amplifier 230 (i.e., the reference bit line). As illustrated in FIG. 2, each sense amplifier has one input coupled to a bit line of array 210a and another input coupled to a corresponding bit line of array 210b. The word line WL13 associated with the CAM cell 100 would then be charged, causing the transistor Q1 in the CAM cell 100 to conduct and thereby share the charge of capacitor CA with bit line BL1. The charge sharing alters the voltage level of bit line BL11. The sense amplifier 230 is then used to detect the change in potential between BL11 and BL21. The sense amplifier outputs an indication of the state stored at storage node A as a signal indicating the relative potential difference between bit lines BL11 and BL21 on line 235.
The performance of the above described read operation suffers from many noise issues since the sensing mechanism relies on the reference and active bit lines to be from two separate arrays of the device during a sensing operation. As CAM devices increase in density and therefore power consumption, the level of noise within a CAM cell is likely to increase. There is therefore a need for a CAM device architecture which has better noise immunity.